HqFpga V1.6 (Winter 2012) 发布

[2013.01.06]

主要更新包括：

- 加强RTL快速综合Verilog语言支持(如task/while语句等)

- 增强逻辑优化与映射功能功能(如嵌入ABC模块等)

详情请参见发布说明：

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HqFpga V1.6 (Winter 2012) Release Note

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The major improvements of this release over last release (V1.5 Winter 2011) include:
o Enhanced Language support for Verilog RTL synthesis, including

  - Task  

  - While  

  - Blackbox

o Improved Verilog RTL synthesis QoR around 20%

o Enchanced LO (Logic Optimization) and MAP(technology mapping) modules:  

  - Integrate ABC LO/MAP packages

  - Add more optimization efforts

o Fxied serveral bugs related with DIFFIO/BRAM and DCM for Virtex2 device family.

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